During the known manufacture of circuitized substrates such as printed circuit boards and chip carriers, especially those of the multilayered type, many individual processes such as etching, plating, lamination, drilling, testing, inspection, etc. are required. These processes are usually performed at different locations within the manufacturing facility, requiring shipment of partially completed substrates from one station to another at such different locations. As defined in the two co-pending applications cited above, it is possible to combine many of these processes while producing a substrate in a continuous roll format; that is, a series of rolls are used to continuously move a common part of the eventual substrate along while such processes are then performed thereon. Such continuous processing, defined therein as in a roll-to-roll format, serves to reduce costs and time consumed in the total substrate manufacturing process. Such savings are especially significant if possible when producing relatively complex, multilayered substrates having several conductive and dielectric layers so that the savings may be passed down to the eventual consumer of the products using such substrates. Such products may include computers, computer servers, mainframes, etc. and many others not related directly to computers.
As is known, these boards typically consist of parallel, planar, alternating inner layers of insulating (dielectric) substrate material and conductive metal. The exposed outer sides of the laminated structure are often provided with circuit patterns, as with double-sided boards, and the metal inner layer or layers typically contain circuit patterns, or, in the case of internal power planes, layers that are substantially solid. These latter layers also often include clearance openings or other openings if desired.
In multilayer printed circuit boards and chip carriers, it is often necessary to provide conductive interconnections between the various conductive layers or sides of the substrate. This is commonly achieved by providing metallized, conductive thru holes in the board which communicate with the sides and layers requiring electrical interconnection. For some applications, it is desired that electrical connection be made between all or almost all of the conductive layers. It is often desired to also provide electrical connection between the circuitry on one face of the board and one or more of the inner circuit layers. In those cases, “blind vias”, passing only part way through the board, are provided. In still another case, such multilayered boards often require internal “vias” which are located entirely within the board's structure and covered by external layering, including both dielectric and conductive. Such internal “vias” are typically formed within a sub-part structure of the final board and then combined with other layers during final lamination of the board. The term “conductive thru-hole” as used in the art may thus include thru holes that pass entirely through the board (also referred to in the printed circuit field as plated thru holes or PTHs), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as an “internal via” which is internally “captured” by the board's outer layers.
To provide the desired circuit pattern on the substrate, a variety of even more manufacturing processes are required, examples being those which fall into the broad categories of “subtractive” or “additive” techniques. Common to subtractive processing is the need to etch away (or subtract) metal to expose substrate surface in areas where no circuitry is desired. Additive processes, on the other hand, begin with exposed substrate surfaces (or thin commoning metallization layers for additive electroplate) and build up thereon of metallization in desired areas, the desired areas being those not masked by a previously-applied pattern of plating resist material (e.g., called photo-resist in the printed circuit board field).
Typically, the dielectric materials used for such multilayered products include some form of supporting material in the form of either fibers or mesh within the dielectric (usually a resin which is cured). Perhaps the most common form of such dielectric material known and used in the industry today is referred to simply as “FR4”, which is comprised of epoxy resin with fiber glass embedded therein. Such fiber glass is typically in the form of continuous or semi-continuous fibers which extend within the cured, hardened resin. Other dielectric materials include polytetrafluoroethylene (e.g., Teflon, a trademark of E.I. du Pont de Nemours & Company) and Driclad material (Driclad is a trademark of the Assignee of this invention, Endicott Interconnect Technologies, Inc.), etc. With such other materials, however, it is also often considered necessary to provide fiber or mesh for reinforcement purposes.
The presence of glass fibers, especially woven glass fibers, also substantially impairs the ability to form high quality, very small thru-holes, including when using a laser. This problem is increased significantly when patterns of such thru holes are required to satisfy the high density requirements of many of today's circuitized substrates, especially those in the computer field. Examples of high density patterns may include thru hole patterns as dense as 5,000 thru holes per square inch and perhaps greater, including in some known examples as high as 10,000 thru holes per square inch, of the substrate's area. If used in such an environment, glass cloth will possess drastically different absorption and heat of ablation properties than typical thermo-set or thermo-plastic matrix resins. In a typical woven glass cloth, for example, the density of glass a laser might encounter can vary from approximately 0% in a window area to approximately 50% by volume or even more, especially in an area over a cloth “knuckle”. This wide variation in encountered glass density leads to problems obtaining the proper laser power for each thru-hole and may result in wide variations in thru-hole quality, obviously unacceptable by today's very demanding manufacturing standards.
The presence of glass fibers in a multilayered structure of the types mentioned herein also often contributes to an electrical failure mode known as CAF growth. CAF (cathodic/anodic filament) growth often results in an electrical shorting failure which occurs when dendritic metal filaments grow along an interface (typically a glass fiber/epoxy resin interface), creating an electrical path between two features which should remain electrically isolated. Whether continuous (like woven cloth) or semi-continuous (like chopped fiber mattes), glass fiber lengths are substantial in comparison to the common distances between isolated internal features, and thus glass fibers can be a significant detractor for PCB insulation resistance reliability. While the use of glass mattes composed of random discontinuous chopped fibers (in comparison to the longer fibers found in continuous structures) can largely abate the problem of inadequate laser drilled thru-hole quality, such mattes still contain fibers with substantial length compared to internal board feature spacing and, in some cases, offer virtually no relief from the problem of this highly undesirable type of growth.
Examples of methods of making circuitized substrates, including multilayered boards, and even further including providing same with such thru holes, are shown and described in the following U.S. Letters Patents, as are examples of various types of boards produced by such methods:
6,015,520Method For Filling Holes in Printed Wiring Boards6,073,344Laser Segmentation of Plated Through-Hole Sidewalls ToForm Multiple Conductors6,175,087Composite Laminate Circuit Structure And Method OfForming The Same6,188,027Protection of a Plated Through Hole From Chemical Attack6,204,453Two Signal One Power Plane Circuit Board6,349,871Process For Reworking Circuit Boards6,388,204Composite Laminate Circuit Structure And Methods OfInterconnecting The Same6,479,093Composite Laminate Circuit Structure And Methods OfInterconnecting The Same6,493,861Interconnected Series of Plated Through Hole Vias andMethod of Fabrication Therefore6,495,239Dielectric Structure And Method Of Formation6,521,844Through Hole In A Photoimageable Dielectric Structure WithWired And Uncured Dielectric6,626,196Arrangement and Method For Degassing Small-High AspectRatio Drilled Holes Prior To Wet Chemical Processing6,628,531Multi-Layer and User-Configurable Micro-Printed CircuitBoard6,630,630Multilayer Printed Wiring Board and Its ManufacturingMethod6,630,743Copper Plated PTH Barrels and Methods For Fabricating6,631,558Blind Via Laser Drilling System6,631,838Method For Fabricating Printed Circuit Board6,638,690Method For Producing Multi-Layer Circuits6,638,858Hole Metal-Filling Method6,750,405Two Signal One Power Plane Circuit Board
As mentioned in the above co-pending applications, attempts have been made to manufacture at least some parts of circuit boards using what might be referred to as a continuous process. Examples of some of these processes are described below. The listing of the patents both above and below is not an admission that any are prior art to the present invention.
In U.S. Pat. No. 4,372,800, issued Feb. 8, 1983, there is described a “continuous” process for producing reinforced resin laminates comprising the steps of impregnating a fibrous substrate with a liquid resin (allegedly free of volatile solvent and capable of curing without generating liquid and gaseous by-products), laminating a plurality of the resin-impregnated substrates into a unitary member, sandwiching the laminate between a pair of covering sheets, and curing the laminate between said pair of covering sheets, without applying appreciable pressure. The patent discusses adjusting the final resin content in the resin impregnated substrate at 10 to 90% by weight, based on the total weight of the impregnated substrate.
In U.S. Pat. No. 4,557,784, issued Dec. 10, 1985; there is described a metal clad laminate produced in “continuous” manner by impregnating a plurality of fibrous substrate with a curable liquid resin, combining the plurality of substrates together and simultaneously laminating a metal foil onto at least one side of said substrates, and curing the laminate. This patent discusses the steps of applying an adhesive onto the metal foil to form a film and heating the film in situ continuously prior to step of the laminating of said metal foil.
In U.S. Pat. No. 4,579,612, issued Apr. 1, 1986, there is described the formation of an “electro-laminate” made of a core of insulating material webs with a high purity electrolytic copper foil on at least one side of the core, for use as a circuit board in electronic equipment. The web of insulating material and the copper foil are led from supply rolls to a laminating machine in out-of-contact relation. Prior to its introduction into the laminating machine, the copper foil is heated to the temperature of the laminating operation so that it is at its maximum thermally expanded length when it contacts the insulating material webs. Further, dust is removed from the copper foil as it enters the laminating machine. The webs and copper foil are moved at the same speed through the laminating machine. After pressing the electro-laminate in the laminating machine, it is moved through a cooling device. Subsequently, the electro-laminate can be wound in a roll or cut into individual lengths.
In U.S. Pat. No. 4,659,425, issued Apr. 21, 1987, there is described a “continuous” method wherein a coating of a solvent-free thermosetting resin is applied to the surface of a metal foil. This resin-coated foil is advanced into contact with a reinforcing cloth sheet layer to form a foil/cloth assembly. The assembly is continuously conveyed between a pair of endless belts revolving in opposite directions with mutually facing surfaces, the belts being heated to the curing temperature of the resin whereby the belts are pressed against the assembly to continuously compact the assembly and cure the resin to form a composite product which can then be circuitized. This partial process does not include many of the essential steps such as defined above which are necessary for boards of more complex construction, especially those needing conductive thru-holes as part thereof.
In U.S. Pat. No. 5,153,986, issued Oct. 13, 1992, there is described a method of fabricating a multilayer electronic circuit package. The multilayer circuit package has at least one layer that is a circuitized, polymer encapsulated metal core. According to the method of the invention a metal foil is provided for the metal core of the layer. This metal core foil may be provided as a single unit or in a roll to roll, process. The thru holes are drilled, etched, or punched through the metal foil. An adhesion promoter is then applied to the perforate metal foil for subsequent adhesion of polymer to the foil. The dielectric polymer is then applied to the perforate metal foil core by vapor depositing, chemical vapor depositing, spraying or electrophoretically depositing, a thermally processable dielectric polymer or precursor thereof onto exposed surfaces of the perforate metal foil including the walls of the thru holes. The dielectric polymer or precursor thereof is then thermally processed to form a conformal dielectric, polymeric coating on surfaces of the perforate metal foil, including the interior surfaces of the thru holes. This dielectric, polymeric coating may then be circuitized, and coated with an adhesive for lamination to the next adjacent layer. After lamination, one or more chips are attached to the completed package.
In U.S. Pat. No. 6,500,349, issued Dec. 31, 2002, there is described a “continuous” process for forming multilayer circuit structures which includes applying and curing a film forming polymer onto the matte side of a copper foil. The opposite (shiny) side of the foil is cleaned, and applied with a photo-resist which is then dried. The photo-resist is exposed, and developed to remove the non-image areas, while leaving the image areas. The foil under the removed non-image area is then etched to form a copper pattern, and the remaining photo-resist is removed. The foil is then cut into sections, and then punched with registration holes. The copper pattern is then treated with a bond enhancing treatment, inspected for defects, and laminated onto a substrate to form a multilayered circuit structure.
The present invention represents a new and unique method of forming circuitized substrates having conductive thru holes therein, in comparison to those above and other processes known in the art. Significantly, the method as defined herein involves the making of a circuitized substrate in which a continuous process is used to form one of the key elements of a sub-composite which will eventually form part of the final composite multilayered substrate along with at least one other (and preferably more) sub-composites, these sub-composites being bonded together to form the final structure. Significantly, thru holes may then be formed which extend entirely through the thickness of the formed composite while using laser ablation to form same, thereby omitting the need for mechanical drilling. The dielectric material for the sub-composites assures effective laser drilling without harm to the dielectric because it does not include glass fibers as part thereof. Thru hole patterns of high density are thus possible. It is believed that such a method will represent a significant advancement in the art.